The workshop is co-located with the 15^th International Symposium on
High-Performance Computer Architecture (HPCA-15) - February 14-18, 2009.

The duration of this workshop is one day.
Please watch this space for program updates. Innovations related to I/O on commercial client and server platforms have largely focused on providing high bandwidth and low latency physical interfaces to processors and memory. USB and PCI represent two interfaces that have evolved over time providing end-users increasing capability in connectivity and functionality. Going forward, I/O may not simply be a physical interconnect issue. As a minimum, I/O is associated with a host controller that decouples processors from I/O related data movement. As the nature of I/O becomes more demanding from the perspective of latency, bandwidth and computational cycles required for I/O processing, the host controllers become increasingly complex. In addition, cost, power and form factor considerations are becoming increasingly important in both client and server systems leading to integration and System-On-Chip designs. For example, Sun UltraSPARC T2 includes a 2x10GbE integrated NIC. System-on-Chip designs are common among low-end mobile platforms and embedded systems. But simple integration may not be the solution either due to die-area or power constraints. In this context, I/O subsystems are highly likely to have a profound influence on the nature of microprocessors going forward.

The workshop solicits original papers on completed work, future directions, position papers, and/or work-in progress papers in the following areas. We encourage all to submit papers that bring out new and interesting approaches even if they are in early stages of development. The main goal is to have leading researchers in academia and industry to meet and put their ideas on the table. Topics of interest include (but are not limited to):

• Historical perspectives on how I/O subsystems have evolved
• Evaluation of existing I/O subsystems and implications
• Microprocessor core/cache architecture enhancements for speeding up I/O processing, I/O related data movement and power management
• Relationships between typical programmable cores, accelerators and I/O (tightly coupled communications and computational accelerators)
• Software-Hardware partitioning of I/O processing
• Influence of I/O subsystem virtualization
• Architectural trade-offs when integrating various forms of I/O (wireless or wired networking, storage, USB and high performance interconnects)
• Integration styles - monolithic integration of existing discrete designs or infusion of I/O into microprocessor cores
• Measurement, modeling and simulation paradigms to improve the evaluation of processor-I/O interaction

Abstract:	December 12th, 2008
Final Paper:	December 19th, 2008
Final Agenda:	January 9th, 2009
Workshop:	February 15th, 2009

The document format of your submission should be in the same format used for the HPCA conference (Microsoft doc format and PDF). All submissions must be in PDF format and are strictly limited to 10 pages. Shorter papers that clearly articulate a position or set a fundamental direction are welcome.

Please submit all papers to: xia.zhu@intel.com

PC Chairs	Ram Huggahalli	Intel Corporation
	Laxmi Bhuyan	University of California Riverside
PC Members	Pavan Balaji	Argonne National Labs
	Nathan Binkert	Hewlett Packard
	Ron Brightwell	Sandia National Labs
	Brad Burres	Intel Corporation
	Patrick Crowley	Washington State University at St Louis
	Gianluca Iannaccone	Intel Research Berkeley
	Steve King	Intel Corporation
	Steve Reinhardt	AMD Corporation
	Tilman Wolf	University of Massachusetts Amherst
	Xia Zhu	Intel Corporation

General Information:	ram.huggahalli@intel.com or bhuyan@cs.ucr.edu
Submissions:	xia.zhu@intel.com
General Workshop Chair:	gbyrd@ncsu.edu