The workshop is co-located with the 15^th International Symposium on
High-Performance Computer Architecture (HPCA-15) - February 14-18, 2009.

Time	Topic and Presenter
8.30 to 9.00	Opening Remarks
9.00 to 9.45	Active End-System Analysis to Estimate the Network I/O Bottleneck Rate Vishal Ahuja, University of California-Davis Rennie Archibald, University of California-Davis Amitabha Banerjee, Sun Microsystems Matt Farrens, University of California-Davis Dipak Ghosal, University of California-Davis
9.45 to 10.30	A Performance Study of Network I/O Accelerators for Network Virtualization Yan Luo, University of Massachusetts-Lowell Chunhui Zhang, University of Massachusetts-Lowell
10.30 to 11.15	Analyzing the Application Performance Impact of Using High-Speed Inter-Socket Communication Networks Douglas Doerfler, Sandia National Laboratories
11.15 to 12.00	Network Interface Cards as First-Class Citizens Wu-chun Feng, Virginia Tech Pavan Balaji, Argonne National Lab Ajeet Singh, Virginia Tech
12.00 to 1.30	Lunch
1.30 to 2.15	High Performance Accelerator Interfacing for Emerging SoC Platforms Yu A Du, University of Pittsburgh Ramesh Illikkal, Intel Corporation Omesh Tickoo, Intel Corporation Li Zhao, Intel Corporation Ravi Iyer, Intel Corporation Don Newell, Intel Corporation
2.15 to 3.00	Architectural Enhancements for Minimizing Message Delivery Latency on Cache-Less Architectures Farshad Khunjush, University of Victoria, Victoria, B.C. Nikitas Dimopoulos, University of Victoria, Victoria, B.C.
3.00 to 3.45	Cache Injection for Private Cache Architectures Florian Auernhammer, IBM Zurich Research Laboratory Patricia Sagmeister, IBM Zurich Research Laboratory
3.45 to 4.30	Exploiting the Produce-Consume Relationship in DMA to Improve I/O Performance Dan Tang, Chinese Academy of Sciences Yungang Bao, Chinese Academy of Sciences Yunji Chen, Chinese Academy of Sciences Weiwu Hu, Chinese Academy of Sciences Mingyu Chen, Chinese Academy of Sciences
4.30 to 5.30	Discussion

Innovations related to I/O on commercial client and server platforms have largely focused on providing high bandwidth and low latency physical interfaces to processors and memory. USB and PCI represent two interfaces that have evolved over time providing end-users increasing capability in connectivity and functionality. Going forward, I/O may not simply be a physical interconnect issue. As a minimum, I/O is associated with a host controller that decouples processors from I/O related data movement. As the nature of I/O becomes more demanding from the perspective of latency, bandwidth and computational cycles required for I/O processing, the host controllers become increasingly complex. In addition, cost, power and form factor considerations are becoming increasingly important in both client and server systems leading to integration and System-On-Chip designs. For example, Sun UltraSPARC T2 includes a 2x10GbE integrated NIC. System-on-Chip designs are common among low-end mobile platforms and embedded systems. But simple integration may not be the solution either due to die-area or power constraints. In this context, I/O subsystems are highly likely to have a profound influence on the nature of microprocessors going forward.

The workshop solicits original papers on completed work, future directions, position papers, and/or work-in progress papers in the following areas. We encourage all to submit papers that bring out new and interesting approaches even if they are in early stages of development. The main goal is to have leading researchers in academia and industry to meet and put their ideas on the table. Topics of interest include (but are not limited to):

• Historical perspectives on how I/O subsystems have evolved
• Evaluation of existing I/O subsystems and implications
• Microprocessor core/cache architecture enhancements for speeding up I/O processing, I/O related data movement and power management
• Relationships between typical programmable cores, accelerators and I/O (tightly coupled communications and computational accelerators)
• Software-Hardware partitioning of I/O processing
• Influence of I/O subsystem virtualization
• Architectural trade-offs when integrating various forms of I/O (wireless or wired networking, storage, USB and high performance interconnects)
• Integration styles - monolithic integration of existing discrete designs or infusion of I/O into microprocessor cores
• Measurement, modeling and simulation paradigms to improve the evaluation of processor-I/O interaction

PC Chairs	Ram Huggahalli	Intel Corporation
	Laxmi Bhuyan	University of California Riverside
PC Members	Pavan Balaji	Argonne National Labs
	Nathan Binkert	Hewlett Packard
	Ron Brightwell	Sandia National Labs
	Brad Burres	Intel Corporation
	Patrick Crowley	Washington State University at St Louis
	Gianluca Iannaccone	Intel Research Berkeley
	Steve King	Intel Corporation
	Steve Reinhardt	AMD Corporation
	Tilman Wolf	University of Massachusetts Amherst
	Xia Zhu	Intel Corporation

General Information:	ram.huggahalli@intel.com or bhuyan@cs.ucr.edu
Submissions:	xia.zhu@intel.com
General Workshop Chair:	gbyrd@ncsu.edu